1. Field of the Invention
The present invention relates to a memory device and a method of fabricating the same and, more particularly, to a DRAM cell, a DRAM memory device and a method of fabricating the DRAM memory device having a plurality of DRAM cells.
2. Description of the Related Art
In general, a DRAM cell provides high capacity and low cost owing to its simple configuration which includes a single transistor and a single capacitor. In this regard, a DRAM cell has been widely used in a variety of electrical products and systems including a computer system. Recently, its application trend has been enlarged widely.
The use of a DRAM cell requires high integration and high capacity in computers which occupies the DRAM market. It also requires increase in the processing speed. However, it is difficult for a conventional DRAM cell having a single transistor and a single capacitor to offer high integration due to limited process technology, such as, optical lithography using an infrared ray, which is generally adopted in fabricating a conventional DRAM cell.
A conventional DRAM cell will now be described with reference to the appended drawings.
FIG. 1 shows a circuit diagram of a conventional DRAM cell. The conventional DRAM cell includes a bitline, a wordline, a single access transistor, a single storage capacitor and a sensing amplifier (not shown). A gate of the access transistor is connected to the wordline. Source and drain electrodes of the access transistor are connected to the storage capacitor and the bitline, respectively. A cell plate electrode of the storage capacitor is connected to a reference voltage. An input port of the sensing amplifier is connected to the bitline and the other port of the amplifier is connected to the reference voltage.
A data from the bitline is stored in the storage capacitor through the source and drain electrodes of the access transistor when the access transistor is in the power-on state. The stored data is transferred to the bitline through the source and drain electrodes when the access transistor is in the power-on state again. A logic value of the data stored in the capacitor is determined by comparing a signal voltage thereon with the reference voltage of the bitline.
The capacitor of the DRAM cell generally includes a storage electrode of n+ poly Si, a plate electrode and a dielectric layer between the storage and plate electrodes.
Data writing and data reading to and from the conventional DRAM cell having a configuration as aforementioned will now be described in detail.
Electrons are redistributed on the surface of the storage electrode under the dielectric layer due to a xc2xd Vcc voltage applied to the plate electrode in case no data is stored in the storage electrode. A depletion layer of the electrons is formed in the interface.
Generally, Vcc voltage is applied to the bitline and the wordline during the writing of data corresponding to logic xe2x80x981xe2x80x99. As a result, a gate electrode voltage and a source electrode voltage of the access transistor increase up to the Vcc voltage level and the access transistor enters the power-on state.
In the storage electrode layer of the storage capacitor, xc2xd Vccxe2x88x92xcex94 voltage, i.e., a voltage xcex94 dropped by the dielectric layer subtracted from the cell plate electrode voltage xc2xd Vcc, is applied. Therefore, since the electrons flow from the storage electrode layer having a high potential to the source electrode having a low potential, the depletion layer is enlarged in the storage electrode layer. In addition, the depletion layer remains in the storage electrode layer if the wordline voltage is dropped to a ground potential voltage. At this state, the stored binary code represents logic xe2x80x981xe2x80x99.
For writing data corresponding to logic xe2x80x980xe2x80x99 in the memory cell, Vcc voltage is applied to the gate of the access transistor using the bitline voltage as a ground potential voltage.
In this case, the electrons flow from the source electrode having a high potential to the storage electrode layer having a low potential since xc2xd Vccxe2x88x92xcex94 voltage in the storage electrode layer is higher than the source electrode voltage xe2x80x980xe2x80x99. As a result, the electrons are accumulated in the storage electrode layer and the depletion layer is restored to an accumulation layer. The electrons remain in the storage electrode layer if the wordline voltage is dropped to the ground voltage. At this state, the stored binary code represents xe2x80x980xe2x80x99.
Data reading of the conventional DRAM cell will be described below.
Vcc voltage is applied to the wordline under the state where the bitline is pre-charged at xc2xd Vcc voltage level. At this time, the access transistor is turned on to the power-on state and the data stored in the storage electrode layer of the capacitor is transferred to the bitline. The voltage of the bitline is varied depending on the stored charge quantity. This varied voltage is compared with the reference voltage of the bitline in a dummy cell, through the sensing amplifier having a function such as a comparator circuit. The voltage difference is amplified so that the logic value is determined to be xe2x80x981xe2x80x99 when the varied voltage of the bitline is higher than the reference voltage. In the alternative, the logic value is determined to be xe2x80x980xe2x80x99 when the varied voltage is lower than the reference voltage.
The voltage difference can be expressed as follows.
xcex94V=(xc2xd)Vcc Cs/(Cs+Cb)
where, Cs is a storage capacitance and Cb is a bitline capacitance.
The error of the logic value is reduced since higher the Cs/Cb ratio is higher the xcex94V voltage is. However, the conventional DRAM cell has several problems.
The difference A between the bitline voltage capable of being discriminated by the sensing amplifier and the reference voltage is about 100-200 mV or more. Thus, the ratio xcex3(xcex3=Cs/Cb) of the storage capacitance for the bitline capacitance should be high. The area of the cell is considerably reduced if the density of the DRAM increases. Nevertheless, the capacity of the bitline and the sensitivity of the sensing amplifier are not improved. Furthermore, it is likely that the signal-to-noise ratio is reduced, and the cell transistor malfunctions.
Moreover, the reliability of the conventional DRAM cell may be degraded by a soft error due to a particle. That is, a pair of electron-holes are formed by ionization impact if a particle comes into collision with the semiconductor substrate. Minority carrier of the electron-holes is captured in the storage electrode to vary the charge quantity stored in the storage electrode. To eliminate such a soft error due to a particle, the area of the storage electrode has to increase in a three-dimensional extent or the dielectric layer having high dielectric ratio has to be formed. But, the electrons deteriorate exposure and etching processes because the electrons have high step differences.
In case of forming the dielectric layer, it is further difficult to achieve high integration of the conventional DRAM cell due to undesired characteristics, such as, a leakage current, a breakdown voltage, and lack of technology in fabricating a thin film.
Accordingly, the present invention is directed to a memory cell, a memory device and a method of fabricating the memory device having at least one memory cell, which substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a memory cell, a memory device and a method of fabricating the memory device and/or memory cell, in which the memory cell includes a transistor, but no separate capacitor, such that the integration and reliability of the memory device is improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a memory cell according to the present invention includes a first gate, a source electrode connected to a bitline, a drain electrode and a second gate, wherein either the first or second gate is connected a wordline, and either the first or second gate, which is not connected to the wordline, is connected to the drain electrode, for writing and reading data of the bitline to and from the first or second gate which is connected to the drain electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
Briefly described, the memory device according to the first embodiment of the present invention includes, a plurality of first and second impurity diffused regions formed on a semiconductor substrate, a gate insulating film formed on the semiconductor substrate between the first and second impurity diffused regions, a second gate formed in contact with the first impurity diffused regions, a dielectric layer formed on the second gate, a first gate formed on the dielectric layer, at least one wordline formed in contact with the first gate, and at least one bitline formed in contact with one of the second impurity diffused regions.
The method of fabricating a memory device according to the first embodiment of the present invention includes the steps of forming at least one first impurity diffused region on a semiconductor substrate; forming a second gate in contact with the one first impurity diffused region, a dielectric layer on the second gate, and a first gate on the dielectric layer; forming at least one wordline in contact with the first gate; forming a second impurity diffused region on the semiconductor substrate; and forming at least one bitline in contact with the second impurity diffused region.
The memory device according to another example of the first embodiment includes a plurality of first and second impurity diffused regions formed on a semiconductor substrate, a second gate formed on the semiconductor substrate between the first and second impurity diffused regions, an oxide film formed in contact with one of the second impurity diffused regions, a contact layer formed in contact with the first impurity diffused regions, a dielectric layer formed on the contact layer, a first gate formed on the dielectric layer, at least one wordline formed in contact with the first gate, and at least one bitline formed in contact with the one second impurity diffused region.
The method of fabricating a memory device according to another example of the first embodiment of the present invention includes the steps of forming a plurality of first and second impurity diffused regions on a semiconductor substrate; forming a second gate on the semiconductor substrate between the first and second impurity diffused regions; forming an oxide film in contact with one of the second impurity diffused regions; forming a contact layer in contact with the first impurity diffused regions, a dielectric layer on the contact layer, and a first gate on the dielectric layer; forming at least one wordline in contact with the first gate; and forming at least one bitline in contact with the one second impurity diffused region.
The memory device according to the second embodiment of the present invention includes a plurality of first and second impurity diffused regions formed on a semiconductor substrate, a second gate formed on the semiconductor substrate between the first and second impurity diffused regions, a dielectric layer formed on the second gate, a first gate formed on the dielectric layer, a first interleave insulting layer formed on the first gate, at least one wordline formed in contact with the second gate through the first interleave insulting layer, and at least one bitline formed in contact with one of the second impurity diffused regions.
The method of fabricating a memory device according to the second embodiment of the present invention includes the steps of forming a plurality of first and second impurity diffused regions on a semiconductor substrate; forming a second gate on the semiconductor substrate between the first and second impurity diffused regions, a dielectric layer on the second gate, and a first gate on the dielectric layer; forming a first interleave insulting layer on the first gate; forming at least one wordline in contact with the second gate through the first interleave insulting layer; and forming at least one bitline in contact with one of the second impurity diffused regions.
The memory device according to another example of the second embodiment of the present invention includes a plurality of first and second impurity diffused regions formed on a semiconductor substrate, a second gate formed on the semiconductor substrate between the first and second impurity diffused regions, a contact layer formed in contact with the second gate, a dielectric layer formed on the contact layer, a first gate formed on the dielectric layer and in contact with one of the first impurity diffused regions, at least one wordline formed on the in contact with the second gate, and at least one bitline formed in contact with the one second impurity diffused region.
The method of fabricating a memory device according to another example of the second embodiment of the present invention includes the steps of forming a plurality of first and second impurity diffused regions on a semiconductor substrate; forming a second gate on the semiconductor substrate between the first and second impurity diffused regions; forming a contact layer in contact with the second gate; forming a dielectric layer on the contact layer; forming a first gate on the dielectric layer and in contact with one of the first impurity diffused regions; forming at least one wordline in contact with the second gate; and forming at least one bitline in contact with one of the second impurity diffused regions.